1. Field of the Invention
The present invention generally relates to a voltage regulator, and more particularly, to a voltage regulator with auto-zeroing technique and unaffected by the load connected to an applied load circuit.
2. Description of Related Art
A voltage regulator is popular electrical device and broadly preferred by many analog circuit designers since it can provide an applied load circuit with a stable output voltage.
FIG. 1 is a schematic circuit drawing of a conventional voltage regulator 100. Referring to FIG. 1, during the operation of the voltage regulator 100, the inverting input terminal (−) of an operational transconductance amplifier (OTA) would receive an input voltage Vi. Besides, the connection node between resistors R1 and R2 has a voltage equal to the input voltage Vi according to the concept of virtual short. Thus, an output voltage VOUT would be generated at the connection node between the resistor R1 and a PMOS transistor P0. After that, a capacitor CL is used to stabilize the output voltage VOUT to feed the stabilized output voltage to a load circuit 101 for use, wherein the above-mentioned output voltage VOUT is just the product voltage of the above-mentioned input voltage Vi and a factor of (1+R1/R2). The R1 and R2 herein are respectively the resistances of the resistors R1 and R2, while the factor of (1+R1/R2) represents the closed-loop gain of the OTA.
Theoretically, the voltage regulator 100 is supposedly to provide a stable output voltage VOUT to the applied load circuit 101. However, due to an unmatched differential input circuit (not shown) in the OTA, an input offset voltage occurs between the inverting input terminal (−) and the non-inverting input terminal (+) of the OTA, which causes the connection node between the resistors R1 and R2 to have a voltage unequal to the input voltage Vi but equal to the sum of the input voltage Vi and an input offset voltage VOS. As a result, the output voltage VOUT provided by the voltage regulator 100 contains a little error provided to the applied load circuit 101, but such an error is not desired by any analog circuit designer.
In order to solve the error problem of the output voltage VOUT provided by the voltage regulator 100 caused from the unmatched differential input circuit in the OTA, a so-called auto-zeroing technique was proposed by the relevant developers in the art.
FIG. 2 is a schematic circuit drawing of a voltage regulator 200, which is evolved from the conventional voltage regulator 100 by employing the auto-zeroing technique. Referring to FIG. 2, the most of the circuit architecture of the voltage regulator 200 is the same as the voltage regulator 100 except the voltage regulator 200 employs an auto-zeroing unit 201, which is able to simultaneously turn on switches SW1 and SW3 and turn off a switch SW2 during a first period; thus, the capacitor CS of the auto-zeroing unit 201 would store a compensation voltage with the same polarity and the same voltage level as the input offset voltage VOS presented between the inverting input terminal (−) and the non-inverting input terminal (+) of the OTA.
Then, the auto-zeroing unit 201 simultaneously turns off the switches SW1 and SW3 and turn on the switch SW2 during a second period; so that the compensation voltage stored in the capacitor CS would counterbalance the input offset voltage VOS presented between the inverting input terminal (−) and the non-inverting input terminal (+) of the OTA, the voltage at the connection node between the resistors R1 and R2 would be equal to the input voltage Vi and the voltage regulator 100 is able to provide an accurate output voltage VOUT without error for the load circuit 101 to use.
Although the auto-zeroing unit 201 of FIG. 2 can theoretically solve the error problem of the output voltage VOUT provided by the voltage regulator 100 caused from the unmatched differential input circuit in the OTA, however, the load effect along with the load circuit 101 has not been considered yet. Considering the load effect along with the load circuit 101, the compensation voltage stored by the capacitor CS of the auto-zeroing unit 201 during the first period would not be exactly the input offset voltage VOS presented between the inverting input terminal (−) and the non-inverting input terminal (+) of the OTA.
The reason for the above-mentioned load effect and the negative impact thereof rests in that when the load current of the load circuit 101 has a transient change, the transient current would be fed back to the non-inverting input terminal (+) through the closed-loop feedback path of the OTA, so that the compensation voltage stored by the capacitor CS of the auto-zeroing unit 201 during the first period would not be exactly the input offset voltage VOS presented between the inverting input terminal (−) and the non-inverting input terminal (+) of the OTA; furthermore during the second period, the compensation voltage stored by the capacitor CS of the auto-zeroing unit 201 during the first period is not able to completely counterbalance the input offset voltage VOS presented between the inverting input terminal (−) and the non-inverting input terminal (+) of the OTA, which results in an error of the output voltage VOUT provided by the voltage regulator 100.